1. Field of the Invention
This invention relates to the field of memory cell layouts. More particularly, this invention relates to the layout of word lines and power conductors within a metal layer of a memory cell.
2. Description of the Prior Art
It is known to provide memory cells which include multiple metal layers. As process geometries shrink, such as to 20 nm, various problems arise that were not encountered in larger process geometries. One example is the constraint upon minimum via spacing. One way of addressing this is to move the word lines into the M1 or M2 layers. However, a problem with this approach is that it results in a larger RC value associated with the word lines and this slows down memory accesses and memory cycle times. Furthermore, the increase in the RC of the memory line will also increase the power consumed and the area of the memory if it is necessary to buffer the word line.